Table 7.10 Floating-Point Double-Precision Instructions
Instruction
Operation
Instruction Code
Privileged T Bit
FABS
DRn
DRn & H'7FFF FFFF FFFF
1111nnn001011101
—
—
FFFF → DRn
FADD
DRm,DRn
DRn + DRm → DRn
1111nnn0mmm00000
1111nnn0mmm00100
—
—
—
FCMP/EQ DRm,DRn
When DRn = DRm, 1 → T
Otherwise, 0 → T
Comparison
result
FCMP/GT DRm,DRn
When DRn > DRm, 1 → T
Otherwise, 0 → T
1111nnn0mmm00101
1111nnn0mmm00011
—
Comparison
result
FDIV
DRm,DRn
DRn /DRm → DRn
—
—
—
—
—
—
—
—
—
—
—
—
FCNVDS DRm,FPUL
FCNVSD FPUL,DRn
double_to_ float[DRm] → FPUL 1111mmm010111101
float_to_ double [FPUL] → DRn 1111nnn010101101
FLOAT
FMUL
FNEG
FPUL,DRn
DRm,DRn
DRn
(float)FPUL → DRn
DRn * DRm → DRn
1111nnn000101101
1111nnn0mmm00010
DRn ^ H'8000 0000 0000 0000 1111nnn001001101
→ DRn
FSQRT
FSUB
FTRC
DRn
1111nnn001101101
1111nnn0mmm00001
1111mmm000111101
—
—
—
—
—
—
DRn
DRn
DRm,DRn
DRm,FPUL
DRn – DRm → DRn
(long) DRm → FPUL
Table 7.11 Floating-Point Control Instructions
Instruction
Operation
Instruction Code
Privileged T Bit
LDS
LDS
Rm,FPSCR
Rm,FPUL
Rm → FPSCR
Rm → FPUL
0100mmmm01101010
0100mmmm01011010
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LDS.L @Rm+,FPSCR
LDS.L @Rm+,FPUL
(Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110
(Rm) → FPUL, Rm+4 → Rm
FPSCR → Rn
0100mmmm01010110
0000nnnn01101010
0000nnnn01011010
0100nnnn01100010
0100nnnn01010010
STS
STS
FPSCR,Rn
FPUL,Rn
FPUL → Rn
STS.L FPSCR,@-Rn
STS.L FPUL,@-Rn
Rn – 4 → Rn, FPSCR → (Rn)
Rn – 4 → Rn, FPUL → (Rn)
Rev. 6.0, 07/02, page 190 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
