Table 7.8 System Control Instructions
Instruction
CLRMAC
CLRS
Operation
Instruction Code
Privileged T Bit
0 → MACH, MACL
0 → S
0000000000101000
0000000001001000
0000000000001000
—
—
—
—
—
0
CLRT
0 → T
LDC
Rm,SR
Rm → SR
0100mmmm00001110 Privileged
0100mmmm00011110
LSB
—
—
—
—
—
—
LSB
—
—
—
—
—
—
LDC
Rm,GBR
Rm → GBR
—
LDC
Rm,VBR
Rm → VBR
0100mmmm00101110 Privileged
0100mmmm00111110 Privileged
0100mmmm01001110 Privileged
0100mmmm11111010 Privileged
0100mmmm1nnn1110 Privileged
0100mmmm00000111 Privileged
LDC
Rm,SSR
Rm → SSR
LDC
Rm,SPC
Rm → SPC
LDC
Rm,DBR
Rm → DBR
LDC
Rm,Rn_BANK
@Rm+,SR
@Rm+,GBR
@Rm+,VBR
@Rm+,SSR
@Rm+,SPC
@Rm+,DBR
Rm → Rn_BANK (n = 0 to 7)
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
(Rm) → SSR, Rm + 4 → Rm
(Rm) → SPC, Rm + 4 → Rm
(Rm) → DBR, Rm + 4 → Rm
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
0100mmmm00010111
—
0100mmmm00100111 Privileged
0100mmmm00110111 Privileged
0100mmmm01000111 Privileged
0100mmmm11110110 Privileged
0100mmmm1nnn0111 Privileged
@Rm+,Rn_BANK (Rm) → Rn_BANK,
Rm + 4 → Rm
LDS
Rm,MACH
Rm,MACL
Rm,PR
Rm → MACH
Rm → MACL
Rm → PR
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LDS
LDS
LDS.L
LDS.L
LDS.L
LDTLB
@Rm+,MACH
@Rm+,MACL
@Rm+,PR
(Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110
(Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110
(Rm) → PR, Rm + 4 → Rm
PTEH/PTEL → TLB
0100mmmm00100110
0000000000111000 Privileged
MOVCA.L R0,@Rn
R0 → (Rn) (without fetching
0000nnnn11000011
—
cache block)
NOP
No operation
0000000000001001
—
—
—
—
—
—
OCBI
@Rn
@Rn
Invalidates operand cache block 0000nnnn10010011
OCBP
Writes back and invalidates
operand cache block
0000nnnn10100011
0000nnnn10110011
0000nnnn10000011
OCBWB @Rn
Writes back operand cache
block
—
—
—
PREF
RTE
@Rn
(Rn) → operand cache
—
—
Delayed branch, SSR/SPC →
0000000000101011 Privileged
SR/PC
Rev. 6.0, 07/02, page 187 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
