3.4.1 Unified TLB (UTLB) Configuration.................................................................... 71
3.4.2 Instruction TLB (ITLB) Configuration ................................................................ 75
3.4.3 Address Translation Method ................................................................................ 75
3.5 MMU Functions ................................................................................................................ 78
3.5.1 MMU Hardware Management ............................................................................. 78
3.5.2 MMU Software Management............................................................................... 78
3.5.3 MMU Instruction (LDTLB)................................................................................. 78
3.5.4 Hardware ITLB Miss Handling............................................................................ 79
3.5.5 Avoiding Synonym Problems .............................................................................. 80
3.6 MMU Exceptions .............................................................................................................. 81
3.6.1 Instruction TLB Multiple Hit Exception .............................................................. 81
3.6.2 Instruction TLB Miss Exception .......................................................................... 82
3.6.3 Instruction TLB Protection Violation Exception.................................................. 83
3.6.4 Data TLB Multiple Hit Exception........................................................................ 84
3.6.5 Data TLB Miss Exception.................................................................................... 84
3.6.6 Data TLB Protection Violation Exception ........................................................... 85
3.6.7 Initial Page Write Exception ................................................................................ 86
3.7 Memory-Mapped TLB Configuration............................................................................... 87
3.7.1 ITLB Address Array............................................................................................. 88
3.7.2 ITLB Data Array 1............................................................................................... 89
3.7.3 ITLB Data Array 2............................................................................................... 90
3.7.4 UTLB Address Array........................................................................................... 90
3.7.5 UTLB Data Array 1.............................................................................................. 92
3.7.6 UTLB Data Array 2.............................................................................................. 93
Section 4 Caches................................................................................................................ 95
4.1 Overview........................................................................................................................... 95
4.1.1 Features ................................................................................................................ 95
4.1.2 Register Configuration ......................................................................................... 96
4.2 Register Descriptions ........................................................................................................ 97
4.3 Operand Cache (OC)......................................................................................................... 99
4.3.1 Configuration ....................................................................................................... 99
4.3.2 Read Operation..................................................................................................... 103
4.3.3 Write Operation.................................................................................................... 104
4.3.4 Write-Back Buffer................................................................................................ 105
4.3.5 Write-Through Buffer .......................................................................................... 105
4.3.6 RAM Mode .......................................................................................................... 106
4.3.7 OC Index Mode.................................................................................................... 107
4.3.8 Coherency between Cache and External Memory ............................................... 107
4.3.9 Prefetch Operation ............................................................................................... 108
4.4 Instruction Cache (IC)....................................................................................................... 108
4.4.1 Configuration ....................................................................................................... 108
4.4.2 Read Operation..................................................................................................... 111
Rev. 6.0, 07/02, page xxii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
