Section
Page
Item
Description
22.3.1 Clock and Control
Signal Timing
850, 851
Table 22.28 Clock and
Control Signal Timing
(HD6417750RF200)
Newly added
852, 853
Table 22.29 Clock and
Control Signal Timing
(HD6417750BP200M,
HD6417750SBP200)
Newly added
854, 855
856, 857
Table 22.30 Clock and
Control Signal Timing
(HD6417750SF200)
Amended
Amended
Table 22.31 Clock and
Control Signal Timing
(HD6417750F167,
HD6417750F167I,
HD6417750SF167,
HD6417750SF167I)
858, 859
Table 22.32 Clock and
Control Signal Timing
(HD6417750SVF133,
HD6417750SVBT133)
Amended
Amended
860, 861
864
Table 22.33 Clock and
Control Signal Timing
(HD6417750VF128)
Figure 22.6 Standby Return Amended
Oscillation Settling Time
(Return by 5(6(7)
865
Figure 22.8 Standby Return Amended
Oscillation Settling Time
(Return by ,5/6–,5/3)
866
Figure 22.10 PLL
Amended
Synchronization Settling Time
in Case of IRL Interrupt
22.3.2 Control Signal Timing 868
Table 22.34 Control Signal
Timing (1)
Table newly added
22.3.3 Bus Timing
880
Figure 22.18 SRAM Bus
Cycle: Basic Bus Cycle (No
Wait, Address Setup/Hold
Time Insertion, AnS = 1,
AnH = 1)
Figure changed and
Note added
881
Figure 22.19 Burst ROM
Bus Cycle (No Wait)
Amended
871, 872
Table 22.35 Bus Timing (1)
Table newly added
Rev. 6.0, 07/02, page xviii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
