Section
Page
Item
Description
Appendix F Synchronous
DRAM Address
Multiplexing Tables
972, 973
(19) BUS 32
SH7750R added
(128M: 4M × 8b × 4) × 4
(SH7750S and SH7750R
only)
(20) BUS 32
(256M: 4M × 16b × 4) × 2
(SH7750S and SH7750R
only)
Appendix H Power-On and
Power-Off Procedures
977 to
979
Newly added
Appendix I Product Code
Lineup
980
Table I.1 SH7750 Series
Product Code Lineup
SH7750R added
Rev. 6.0, 07/02, page xx of I