Table 7.4 Arithmetic Operation Instructions (cont)
Instruction
Operation
Instruction Code
Privileged T Bit
EXTS.W
Rm,Rn
Rm,Rn
Rm sign-extended from
word → Rn
0110nnnnmmmm1111
—
—
—
—
—
—
—
—
EXTU.B
Rm zero-extended from
byte → Rn
0110nnnnmmmm1100
0110nnnnmmmm1101
EXTU.W Rm,Rn
Rm zero-extended from
word → Rn
MAC.L
MAC.W
MUL.L
@Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → 0000nnnnmmmm1111
MAC
Rn + 4 → Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
@Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → 0100nnnnmmmm1111
—
—
MAC
Rn + 2 → Rn, Rm + 2 → Rm
16 × 16 + 64 → 64 bits
Rm,Rn
Rn × Rm → MACL
32 × 32 → 32 bits
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
—
—
—
—
—
—
MULS.W Rm,Rn
MULU.W Rm,Rn
Signed, Rn × Rm → MACL
16 × 16 → 32 bits
Unsigned, Rn × Rm → MACL
16 × 16 → 32 bits
NEG
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
0 – Rm → Rn
—
—
—
—
—
—
NEGC
SUB
0 – Rm – T → Rn, borrow → T 0110nnnnmmmm1010
Rn – Rm → Rn
0011nnnnmmmm1000
Borrow
—
SUBC
SUBV
Rn – Rm – T → Rn, borrow → T 0011nnnnmmmm1010
Rn – Rm → Rn, underflow → T 0011nnnnmmmm1011
Borrow
Underflow
Rev. 6.0, 07/02, page 183 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
