7.3
Instruction Set
Table 7.2 shows the notation used in the following SH instruction list.
Table 7.2 Notation Used in Instruction List
Item
Format
Description
Instruction
mnemonic
OP.Sz SRC, DEST OP:
Sz:
Operation code
Size
SRC:
Source
DEST: Source and/or destination operand
Summary of
operation
→, ←:
(xx):
Transfer direction
Memory operand
M/Q/T: SR flag bits
&:
|:
Logical AND of individual bits
Logical OR of individual bits
:
~:
Logical exclusive-OR of individual bits
Logical NOT of individual bits
<<n, >>n:n-bit shift
Instruction code MSB ↔ LSB
mmmm: Register number (Rm, FRm)
nnnn:
0000:
0001:
:
Register number (Rn, FRn)
R0, FR0
R1, FR1
1111:
mmm:
nnn:
000:
001:
:
R15, FR15
Register number (DRm, XDm, Rm_BANK)
Register number (DRm, XDm, Rn_BANK)
DR0, XD0, R0_BANK
DR2, XD2, R1_BANK
111:
mm:
nn:
DR14, XD14, R7_BANK
Register number (FVm)
Register number (FVn)
FV0
00:
01:
FV4
10:
FV8
11:
FV12
iiii:
dddd:
Immediate data
Displacement
Privileged mode
“Privileged” means the instruction can only be executed
in privileged mode.
T bit
Value of T bit after
instruction execution
—: No change
Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand(s).
Rev. 6.0, 07/02, page 179 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
