7.2
Addressing Modes
Addressing modes and effective address calculation methods are shown in table 7.1. When a
location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated
into a physical memory address. If multiple virtual memory space systems are selected
(MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID. See
section 3, Memory Management Unit (MMU).
Table 7.1 Addressing Modes and Effective Addresses
Addressing Instruction
Calculation
Formula
Mode
Format
Effective Address Calculation Method
Register
direct
Rn
Effective address is register Rn.
(Operand is register Rn contents.)
—
Register
indirect
@Rn
Effective address is register Rn contents.
Rn → EA
(EA: effective
address)
Rn
Rn
Register
indirect
with post-
increment
@Rn+
Effective address is register Rn contents.
A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand, 8 for a
quadword operand.
Rn → EA
After
instruction
execution
Byte:
Rn + 1 → Rn
Rn
Rn + 1/2/4/8
Rn
Word:
Rn + 2 → Rn
+
Longword:
Rn + 4 → Rn
1/2/4/8
Quadword:
Rn + 8 → Rn
Register
indirect
with pre-
decrement
@–Rn
Effective address is register Rn contents,
decremented by a constant beforehand:
1 for a byte operand, 2 for a word operand,
4 for a longword operand, 8 for a quadword
operand.
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn
Rn – 4 → Rn
Rn – 1/2/4/8
Quadword:
Rn – 8 → Rn
–
Rn – 1/2/4/8
Rn → EA
(Instruction
executed
1/2/4/8
with Rn after
calculation)
Rev. 6.0, 07/02, page 175 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
