Table 7.4 Arithmetic Operation Instructions
Instruction
ADD
Operation
Instruction Code
Privileged T Bit
Rm,Rn
#imm,Rn
Rm,Rn
Rm,Rn
Rn + Rm → Rn
Rn + imm → Rn
0011nnnnmmmm1100
0111nnnniiiiiiii
—
—
—
—
—
—
ADD
—
ADDC
ADDV
Rn + Rm + T → Rn, carry → T 0011nnnnmmmm1110
Carry
Overflow
Rn + Rm → Rn, overflow → T
0011nnnnmmmm1111
10001000iiiiiiii
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
When R0 = imm, 1 → T
Otherwise, 0 → T
Comparison
result
When Rn = Rm, 1 → T
Otherwise, 0 → T
0011nnnnmmmm0000
0011nnnnmmmm0010
—
—
Comparison
result
When Rn ≥ Rm (unsigned),
1 → T
Comparison
result
Otherwise, 0 → T
CMP/GE Rm,Rn
When Rn ≥ Rm (signed), 1 → T 0011nnnnmmmm0011
Otherwise, 0 → T
—
—
Comparison
result
CMP/HI
Rm,Rn
When Rn > Rm (unsigned),
1 → T
0011nnnnmmmm0110
Comparison
result
Otherwise, 0 → T
CMP/GT Rm,Rn
When Rn > Rm (signed), 1 → T 0011nnnnmmmm0111
Otherwise, 0 → T
—
—
—
—
Comparison
result
CMP/PZ
CMP/PL
Rn
Rn
When Rn ≥ 0, 1 → T
Otherwise, 0 → T
0100nnnn00010001
0100nnnn00010101
0010nnnnmmmm1100
Comparison
result
When Rn > 0, 1 → T
Otherwise, 0 → T
Comparison
result
CMP/STR Rm,Rn
When any bytes are equal,
1 → T
Comparison
result
Otherwise, 0 → T
DIV1
Rm,Rn
Rm,Rn
1-step division (Rn ÷ Rm)
0011nnnnmmmm0100
0010nnnnmmmm0111
—
—
Calculation
result
DIV0S
DIV0U
MSB of Rn → Q,
MSB of Rm → M, M^Q → T
Calculation
result
0 → M/Q/T
0000000000011001
0011nnnnmmmm1101
—
—
0
DMULS.L Rm,Rn
Signed, Rn × Rm → MAC,
32 × 32 → 64 bits
—
DMULU.L Rm,Rn
Unsigned, Rn × Rm → MAC,
32 × 32 → 64 bits
0011nnnnmmmm0101
0100nnnn00010000
—
—
—
DT
Rn
Rn – 1 → Rn; when Rn = 0,
1 → T
Comparison
result
When Rn ≠ 0, 0 → T
EXTS.B
Rm,Rn
Rm sign-extended from
0110nnnnmmmm1110
—
—
byte → Rn
Rev. 6.0, 07/02, page 182 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
