In future version of SH series, the above error is guaranteed, but the same result as SH7750 is not
guaranteed.
FIPR FVm, FVn (m, n: 0, 4, 8, 12): This instruction is basically used for the following purposes:
•
•
Inner product (m ≠ n):
This operation is generally used for surface/rear surface determination for polygon surfaces.
Sum of square of elements (m = n):
This operation is generally used to find the length of a vector.
Since approximate-value computations are performed to enable high-speed computation, the
inexact exception (I) bit in the cause field and flag field is always set to 1 when an FIPR
instruction is executed. Therefore, if the corresponding bit is set in the enable field, enable
exception handling will be executed.
FTRV XMTRX, FVn (n: 0, 4, 8, 12): This instruction is basically used for the following
purposes:
•
Matrix (4 × 4) vector (4):
This operation is generally used for viewpoint changes, angle changes, or movements called
vector transformations (4-dimensional). Since affine transformation processing for angle +
parallel movement basically requires a 4 × 4 matrix, the SH7750 Series supports 4-dimensional
operations.
•
Matrix (4 × 4) × matrix (4 × 4):
This operation requires the execution of four FTRV instructions.
Since approximate-value computations are performed to enable high-speed computation, the
inexact exception (I) bit in the cause field and flag field is always set to 1 when an FTRV
instruction is executed. Therefore, if the corresponding bit is set in the enable field, enable
exception handling will be executed. For the same reason, it is not possible to check all data types
in the registers beforehand when executing an FTRV instruction. If the V bit is set in the enable
field, enable exception handling will be executed.
FRCHG: This instruction modifies banked registers. For example, when the FTRV instruction is
executed, matrix elements must be set in an array in the background bank. However, to create the
actual elements of a translation matrix, it is easier to use registers in the foreground bank. When
the LDC instruction is used on FPSCR, this instruction expends 4 to 5 cycles in order to maintain
the FPU state. With the FRCHG instruction, an FPSCR.FR bit modification can be performed in
one cycle.
Rev. 6.0, 07/02, page 171 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
