P4 Area: The P4 area is mapped onto SH7750 Series on-chip I/O channels. This area cannot be
accessed using the cache. The P4 area is shown in detail in figure 3.4.
H'E000 0000
Store queue
H'E400 0000
Reserved area
H'F000 0000
Instruction cache address array
H'F100 0000
Instruction cache data array
H'F200 0000
Instruction TLB address array
H'F300 0000
Instruction TLB data arrays 1 and 2
H'F400 0000
Operand cache address array
H'F500 0000
Operand cache data array
H'F600 0000
Unified TLB address array
H'F700 0000
Unified TLB data arrays 1 and 2
H'F800 0000
Reserved area
H'FC00 0000
Control register area
Figure 3.4 P4 Area
The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues
(SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the
MMUCR.SQMD bit. For details, see section 4.7, Store Queues.
The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache
address array. For details, see section 4.5.1, IC Address Array.
The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data
array. For details, see section 4.5.2, IC Data Array.
The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB
address array. For details, see section 3.7.1, ITLB Address Array.
Rev. 6.0, 07/02, page 66 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
