The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data
arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2.
The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address
array. For details, see section 4.5.3, OC Address Array.
The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data
array. For details, see section 4.5.4, OC Data Array.
The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address
array. For details, see section 3.7.4, UTLB Address Array.
The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1
and 2. For details, see sections 3.7.5, UTLB Data Array 1, and 3.7.6, UTLB Data Array 2.
The area from H'FF00 0000 to H'FFFF FFFF is the on-chip peripheral module control register
area. For details, see appendix A, Address List.
3.3.2
External Memory Space
The SH7750 Series supports a 29-bit external memory space. The external memory space is
divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM,
synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13,
Bus State Controller (BSC).
H'0000 0000
Area 0
H'0400 0000
Area 1
H'0800 0000
Area 2
H'0C00 0000
Area 3
H'1000 0000
Area 4
H'1400 0000
Area 5
H'1800 0000
Area 6
H'1C00 0000
Area 7 (reserved area)
H'1FFF FFFF
Figure 3.5 External Memory Space
Rev. 6.0, 07/02, page 67 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
