External
memory space
H'0000 0000
H'0000 0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
P0 area
Cacheable
U0 area
Cacheable
H'8000 0000
H'A000 0000
H'C000 0000
H'8000 0000
P1 area
Cacheable
P2 area
Non-cacheable
Address error
P3 area
Cacheable
H'E000 0000
H'E400 0000
H'E000 0000
H'FFFF FFFF
Store queue area
Address error
P4 area
Non-cacheable
H'FFFF FFFF
Privileged mode
User mode
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
In the SH7750, the CPU cannot access a PCMCIA interface area. When performing access from
the CPU to a PCMCIA interface area in the SH7750S or the SH7750R, access is always
performed using the values of the SA and TC bits set in the PTEA register.
The PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn,
CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC. For details, see section 14, Direct
Memory Access Controller (DMAC).
P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or
not the cache is used is determined by the cache control register (CCR). When the cache is used,
with the exception of the P1 area, switching between the copy-back method and the write-through
method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified
by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding
external memory space address. However, since area 7 in the external memory space is a reserved
area, a reserved area also appears in these areas.
P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3
bits of an address gives the corresponding external memory space address. However, since area 7
in the external memory space is a reserved area, a reserved area also appears in this area.
Rev. 6.0, 07/02, page 65 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
