CLOCK GENERATING CIRCUIT
4.2 Clocks
4.2.1 Clocks generated in clock generating circuit
(1) fXIN
It is the input clock from pin XIN
.
(2) fPLL
It is the output clock from the PLL frequency multiplier.
(3) fsys
It is the system clock which becomes the clock source of CPU, BIU, and internal peripheral devices.
Whether fXIN = fsys or fPLL = fsys can be selected by software.
(4) φCPU
It is the operating clock of CPU.
(5) φBIU
It is the operating clock of BIU.
(6) Clock φ
1
It has the same period as fsys
.
(7) f
1
, f
2
, f16, f64, f512, f4096
Each of them is the internal peripheral device’s operating clock.
(8) Wf32, Wf512
These are the operating clocks of the watchdog timer, and their clock source is f
2
.
(9) fX16, fX32, fX64, fX128
Each of them is the divide clock of fXIN and becomes the watchdog timer’s clock source at STP
termination.
7906 Group User’s Manual Rev.2.0
4-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
