RESET
3.3 State of internal area
3.3 State of internal area
Figure 3.3.1 shows the state of CPU registers immediately after reset. Figures 3.3.2 to 3.3.9 show the state
of the SFR and internal RAM areas immediately after reset.
: “0” immediately after reset.
Fix this bit to “0.”
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after reset.
0
0
1
?
Register name
State immediately after reset
b8 b7
b15
b0
b0
b0
b0
b0
b0
b0
b0
Accumulator A (A)
?
?
?
?
?
b15
b8 b7
b8 b7
b8 b7
b8 b7
Accumulator B (B)
?
b15
Index register X (X)
?
b15
Index register Y (Y)
?
b15
Stack pointer (S)
0F16
FF16
b7
b7
Data bank register (DT)
0016
Program bank register (PG)
0016
b15
b8 b7
Program counter (PC)
Contents at address FFFF16
Contents at address FFFE16
b15
b8 b7
b0
Direct page register 0 (DPR0)
0016
?
0016
?
b15
b8 b7
b0
Direct page register i (DPRi)
(i = 1 to 3)
b8 b7
b0
?
b15
0
Processor status register (PS)
0
0
0
0
1
I
0
0
0
0
0
0
?
?
?
Z
IPL
N
V
C
m
x
D
Fig. 3.3.1 State of CPU registers immediately after reset
7906 Group User’s Manual Rev.2.0
3-6
RENESAS [ RENESAS TECHNOLOGY CORP ]
