RESET
3.1 Reset operation
3.1.2 Software reset
The microcomputer initializes pins, CPU, and SFR area just as in the case of hardware reset (Refer to
sections “3.2 Pin state” and “3.3 State of internal area”) by writing “1” to the software reset bit. (See
Figure 3.1.2.)
After initialization is completed, the microcomputer performs “Internal processing sequence after reset.”
(Refer to section “3.4 Internal processing sequence after reset.”) After that, it executes a program
beginning with the address which has been set into the reset vector addresses (addresses FFFE16 and
FFFF16).
b7 b6 b5 b4 b3 b2 b1 b0
Processor mode register 0 (Address 5E16)
0
X X 0 0
Bit
0
Bit name
Function
At reset
R/W
RW
b1 b0
Processor mode bits
0
0
0
0 0 : Single-chip mode
0 1 : Do not select.
1 0 : Do not select.
1 1 : Do not select.
RW
1
Any of these bits may be either “0” or “1.”
RW
RW
RW
2
3
4
1
0
b5 b4
Interrupt priority detection time
0 0 : 7 cycles of fsys
select bits
0 1 : 4 cycles of fsys
1 0 : 2 cycles of fsys
1 1 : Do not select.
0
RW
5
The microcomputer is reset by writing “1” to this
bit. The value is “0” at reading.
Software reset bit
0
0
WO
RW
6
7
Fix this bit to “0.”
X: It may be either “0” or “1”.
Fig. 3.1.2 Structure of processor mode register 0
7906 Group User’s Manual Rev.2.0
3-3
RENESAS [ RENESAS TECHNOLOGY CORP ]
