APPENDIX
Appendix 2. Control registers
b7 b6 b5 b4 b3 b2 b1 b0
At reset R/W
Flash memory control register (Address 9E16)
Bit
0
Bit name
RY/BY status bit
Function
Reference
19-10
19-11
0 : BUSY (Automatic programming or erase operation
is active.)
1
RO
1 : READY (Automatic programming or erase operation
has been completed.)
0
RW
(Notes 1, 2)
0 : Flash memory CPU reprogramming mode is invalid.
1 : Flash memory CPU reprogramming mode is valid.
1
CPU reprogramming mode select bit
0
0
—
The value is “0” at reading.
2
3
Writing “1” into this bit discontinues the access to the
internal flash memory. This causes the built-in flash
memory circuit being reset.
RW
(Note 4)
Flash memory reset bit (Note 3)
—
0
0
The value is “0” at reading.
User ROM area select bit
4
5
0 : Access to boot ROM area
RW
(Note 2)
(Valid in boot mode)
(Note 5) 1 : Access to user ROM area
—
0
7, 6
The value is “0” at reading.
Notes 1: In order to set this bit to “1,” write “0” followed with “1” successively; while in order to clear this bit “0,” write “0.”
2: Writing to this bit must be performed in an area other than the internal flash memory.
3: This bit is valid when the CPU reprogramming mode select bit (bit 1) = “1”: on the other hand, when the CPU
reprogramming mode select bit = “0,” be sure to fix this bit to “0.” Rewriting of this bit must be performed with the CPU
reprogramming mode select bit = “1.”
4: After writing of “1” to this bit, be sure to confirm the RY/BY status bit (bit 0) becomes “1”; and then, write “0” to this bit.
5: When MD1 = Vss level, this bit is invalid. (It may be either “0” or “1.”)
7906 Group User’s Manual Rev.2.0
20-36
RENESAS [ RENESAS TECHNOLOGY CORP ]
