STOP AND WAIT MODES
15.3 Stop mode
Before executing the STP instruction, be sure to enable an interrupt which is to be used for the stop mode
termination.
Also, make sure that the interrupt priority level of an interrupt, which is to be used for the termination, is
higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed.
After oscillation starts (❈), there is a possibility that each interrupt request occurs until the supply of φCPU
,
φBIU starts (❈). The interrupt requests which occurred during this period are accepted in order of priority
after the watchdog timer’s MSB becomes “0.” (When the level sense of an INT interrupt is used, however,
i
no interrupt request is retained. Therefore, if pin INT is at the invalid level when the watchdog timer’s MSB
i
becomes “0,” no interrupt request is accepted.) For an interrupt which has no need to be accepted, be sure
to set its interrupt priority level to “0” (Interrupt disabled) before executing the STP instruction.
15.3.2 Terminate operation at interrupt request occurrence (when not using watchdog timer)
At the stop mode termination, an instruction is executed without use of the watchdog timer. (See Figure
15.3.1.)
❈ When an interrupt request occurs, clock input from pin XIN starts. Simultaneously, supply of clocks fsys
, f
,
φ1
1
to f4096, Wf32, Wf512 starts.
❈ Supply of φCPU, φBIU starts after the time listed in Table 15.3.2 has elapsed.
❈ The interrupt request which occurred in ❈ is accepted.
Table 15.3.2 Time after stop mode is terminated
until supply of φCPU, φBIU starts
Watchdog timer clock source
Time until supply of
select bits at STP termination
(bits 7, 6 at address 6116)
φCPU and φBIU starts
fXIN ❈ 19 cycles
fXIN ❈ 11 cycles
fXIN ❈ 67 cycles
fXIN ❈ 35 cycles
00
01
10
11
Before executing the STP instruction, be sure to set as follows:
❈ Enable an interrupt which is to be used for the stop mode termination.
Also, make sure that the interrupt priority level of an interrupt, which is to be used for the termination,
is higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is
executed.
❈ The external clock input select bit (bit 1 at address 6216) = “1” (Note)
❈ The system clock select bit (bit 5 at address BC16) = “0” (Note)
Note: Simultaneously, the oscillation driver circuit between pins XIN and XOUT stops, and the output level
at pin XOUT is kept “H.” (Refer to section “16.3 Stop of oscillation circuit.”)
7906 Group User’s Manual Rev.2.0
15-9
RENESAS [ RENESAS TECHNOLOGY CORP ]
