STOP AND WAIT MODES
15.4 Wait mode
15.4 Wait mode
When the WIT instruction is executed, both of φCPU and φBIU become inactive. (The oscillation does not
become inactive.) This state is called “wait mode.” (See Table 15.1.1.)
In the wait mode, the power consumption can be saved with Vcc (the power source voltage) retained. When
using no internal peripheral device in the wait mode, the power consumption can be saved furthermore since
each of fsys and internal peripheral device’s operation clock can be inactive. (Refer to section “16.2 Stop
of system clock in wait mode.”)
The wait mode is terminated owing to an interrupt request occurrence or hardware reset.
The wait mode terminate operation is described below.
15.4.1 Terminate operation at interrupt request occurrence
❈ When an interrupt request occurs, each supply of φCPU and φBIU starts.
❈ The interrupt request which occurred in ❈ is accepted.
Table 15.4.1 lists the interrupts which can be used for the wait mode termination.
Table 15.4.1 Interrupts which can be used for wait mode termination
Usage conditions for interrupt request occurrences
Interrupt
System clock in action
System clock out of action
In event counter mode
INTi interrupt (i = 3 to 7)
Timer Ai interrupt (i = 0 to 2, 4, 9)
Timer Bi interrupt (i = 0 to 2)
UARTi transmit interrupt (i = 0, 1)
UARTi receive interrupt (i = 0, 1)
A-D conversion interrupt
When an external clock is selected.
Do not use.
Notes 1: When multiple interrupts are enabled, the wait mode is terminated owing to the interrupt request which
occurs first.
2: For interrupts, refer to “CHAPTER 6. INTERRUPTS” and each peripheral device’s chapter.
Before executing the WIT instruction, be sure to enable an interrupt which is to be used for the wait mode
termination.
Also, make sure that the interrupt priority level of an interrupt, which is to be used for termination, is higher
than the processor interrupt priority level (IPL) of a routine where the WIT instruction is executed.
Also, when multiple interrupts in Table 15.4.1 are enabled, the wait mode is terminated owing to the
interrupt request which occurs first.
15.4.2 Terminate operation at hardware reset
Although each of the CPU and SFR area is initialized, the contents of the internal RAM immediately before
the WIT instruction execution are retained. The terminate sequence is the same as the internal processing
sequence after reset.
For reset, refer to “CHAPTER 3. RESET.”
Also, the WIT-instruction-execution status bit (bit 1 at address 6316) is used for the following verification:
• Which of the power-on reset and hardware reset has been used to reset the system?
• Has the hardware reset been used for the wait mode termination?
7906 Group User’s Manual Rev.2.0
15-12
RENESAS [ RENESAS TECHNOLOGY CORP ]
