STOP AND WAIT MODES
15.3 Stop mode
15.3.3 Terminate operation at hardware reset
Although each of the CPU and SFR area is initialized, the contents of the internal RAM immediately before
the STP instruction execution are retained. The terminate sequence is the same as the internal processing
sequence after reset.
For reset, refer to “CHAPTER 3. RESET.”
Also, the STP-instruction-execution status bit (bit 0 at address 6316) is used for the following verification:
• Which of the power-on reset and hardware reset has been used to reset the system?
• Has the hardware reset been used for the stop mode termination?
7906 Group User’s Manual Rev.2.0
15-11
RENESAS [ RENESAS TECHNOLOGY CORP ]
