PULSE OUTPUT PORT MODE
9.2 Block description
9.2.2 Three-phase output data registers 0, 1
Figure 9.2.3 shows the structures of three-phase output data registers 0, 1 (in the pulse output port mode).
b7 b6 b5 b4 b3 b2 b1 b0
Three-phase output data register 0 (Address A816
)
Bit
0
Bit name
Function
At reset R/W
RTP0
RTP0
RTP0
0
1
2
pulse output data bit
0
0
0
0
0
RW
RW
RW
RW
RW
0 : “L” level output
1 : “H” level output
pulse output data bit
pulse output data bit
1
2
3
RTP0
RTP1
3
0
pulse output data bit
pulse output data bit
(Valid in pulse mode 1.) (Note) 1 : “H” level output
0 : “L” level output
4
5
RTP1 pulse output data bit
(Valid in pulse mode 1.) (Note)
1
0
0
RW
RW
b7 b6
Pulse output trigger select bits
7, 6
0 0 : Underflow of timer A0
0 1 : Falling edge of input signal to pin RTPTRG0
1 0 : Rising edge of input signal to pin RTPTRG0
1 1 : Both falling and rising edges of input signal to
pin RTPTRG0
Note: Invalid in pulse mode 0.
b7 b6 b5 b4 b3 b2 b1 b0
Three-phase output data register 1 (Address A916
)
X X
Bit
0
Bit name
Function
At reset R/W
Pulse width modulation enable
bit 0
0 : No pulse width modulation by timer A1
1 : Pulse width modulation by timer A1
0
0
0
0
0
RW
RW
RW
RW
RW
0 : No pulse width modulation by timer A2
1 : Pulse width modulation by timer A2
Pulse width modulation enable
bit 1
1
2
0 : No pulse width modulation by timer A4
1 : Pulse width modulation by timer A4
Pulse width modulation enable
bit 2
Pulse output polarity select bit
0 : Positive
1 : Negative
3
4
RTP1
0
pulse output data bit
(Valid in pulse mode 0) (Note)
0 : “L” level output
1 : “H” level output
5
RTP1
1
pulse output data bit
0
RW
(Valid in pulse mode 0) (Note)
Invalid in pulse output port mode.
6
7
0
0
RW
RW
X: It may be either “0” or “1.”
Note: Invalid in pulse mode 1.
Fig. 9.2.3 Structures of three-phase output data registers 0, 1 (in pulse output port mode)
7906 Group User’s Manual Rev.2.0
9-6
RENESAS [ RENESAS TECHNOLOGY CORP ]
