PULSE OUTPUT PORT MODE
9.2 Block description
9.2.3 Port P2 direction register, Port P7 direction register
Figure 9.2.4 shows the structure of the port P2 pin function control register; Figure 9.2.5 shows the
relationship between the port P2/P7 direction register and pulse output trigger input pins.
The allocation of the pulse output trigger input pin can be changed by the pin INT
3
/RTPTRG0 select bit.
When using pin P7 (P2 )/RTPTRG0 as a pulse output trigger input pin, be sure to clear the corresponding
4
7
bit of the direction register of the port, which is multiplexed with pin RTPTRG0, in order to set this port pin
for the input mode.
b7 b6 b5 b4 b3 b2 b1 b0
Port P2 pin function control register (Address AE16
)
0
Bit
0
Bit name
Function
At reset R/W
0
RW
Pin TB0IN select bit
0 : Allocate pin TB0IN to P5
1 : Allocate pin TB0IN to P2
5
.
.
4
Pin TB1IN select bit
Pin TB2IN select bit
0 : Allocate pin TB1IN to P5
1 : Allocate pin TB1IN to P2
6
.
.
1
2
3
0
0
0
RW
RW
RW
5
0 : Allocate pin TB2IN to P5
1 : Allocate pin TB2IN to P2
7
.
.
6
Pin INT3/RTPTRG0 select bit
0: Allocate pin INT
1: Allocate pin INT
3
/RTPTRG0 to P7
4
7
.
.
(Note)
3/RTPTRG0 to P2
6 to 4
7
Nothing is assigned.
Undefined
—
0
RW
Fix this bit to “0.”
Note: When allocating pin INT
3
/RTPTRG0 to P7
4
, be sure that the D-A output enable bit (bit 1 at address 9616) = “0” (output
1
disabled).
Fig. 9.2.4 Structure of port P2 pin function control register
7906 Group User’s Manual Rev.2.0
9-9
RENESAS [ RENESAS TECHNOLOGY CORP ]
