RTL8306SD/RTL8306SDM
Datasheet
Pin Name
Pin
No.
Type Drive Description
(MA)
Default
PHY 2
76
I/O
4
Input upon reset in all modes.
1
PRXD[1]/
M(R)2TXD[1]/
GXENFC
(IPU)
The pin is strapping pin GYENFC.
To enable Flow Control ability of GROUP Y:
1: Enable Reg4.10 (NWAY Full duplex only), or ‘Enable
Force Full pause ability of Force Mode (UTP Force Mode)’,
or ‘Enable Force Half Back Pressure ability of Force Mode
(UTP Force Mode)’.
0: Disable Reg4.10 (NWAY Full duplex only), or ‘Disable
Force Full pause ability of Force Mode (UTP Force Mode)’,
or ‘Disable Force Half Back Pressure ability of Force Mode
(UTP Force Mode)’.Strap after reset for initial value of
Group X ‘UTP NWAY Full’, or ‘UTP Force Full or Half
Mode’.
After reset:
When MII/RMII 2 is not enabled; this pin is not used.
When MII/RMII 2 is enabled for PHY4 or MAC5:
For MAC mode MII, this pin is output pin M2TXD[1].
For PHY mode MII, this pin is output pin PHY2PRXD[1].
For RMII mode; this pin is output pin R2TXD[1].
PHY 2PRXD[0]/
M2TXD[0]/
R2TXD[0]/
73
I/O
(IPU)
4
Input upon reset in all modes.
The pin is strapping pin Enable EEPROM:
Sets the RTL8306SD/RTL8306SDM to enable loading of
the serial EEPROM upon reset.
1: Enable
1
ENEEPROM
0: Disable
Output after reset.
When MII/RMII 2 is not enabled; this pin is not used.
When MII/RMII 2 is enabled for PHY4 or MAC5:
For MAC mode MII; this is output pin M2TXD[0].
For PHY mode MII; this is output pin PHY2PRXD[1].
For RMII mode; this is output pin R2TXD[1].
6-Port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller
21
Track ID: JATR-1076-21 Rev. 1.1