RTL8306SD/RTL8306SDM
Datasheet
6.5. Miscellaneous Pins
Table 6. Miscellaneous Pins
Drive
(mA)
Pin Name
Pin No. Type
Description
X1
120
I
-
25MHz crystal input.
The clock tolerance is ±50ppm.
When using an oscillator, this pin should be tied to ground.
For crystal input
When using an oscillator, this pin should be left floating.
X2
121
117
O
I
-
-
OSCI
A 25MHz clock from an oscillator is fed to this pin.
X1 should be tied to ground and X2 should be left floating in this
application.
If the 25MHz clock is from a crystal via X1 and X2, this pin should be
left floating.
CK25MOUT
RESET#
116
40
O
I
8
-
25MHz clock output.
This pin is used to support an extra 25M clock for an external device
(for example: HomePNA PHY).
Note: The default status of the 25MHz clock output is disabled. It can be
enabled through a register setting.
Active low reset signal.
To complete the reset function, this pin must be asserted for at least 1ms.
After reset, about 30ms is needed for the RTL8306SD/RTL8306SDM to
complete internal test functions and initialization.
This pin is a Schmitt input.
IBREF
127
123
A
O
-
Control transmit output waveform Vpp.
This pin should be grounded through a 1.96KΩ resistor.
VCTRL
4
Voltage control to external regulator.
This signal controls a power PNP transistor to generate the 1.8V power
supply.
ITEST1
ITEST2
ITEST3
ITEST4
ITEST5
ITEST6
DTEST2
DTEST1
36
37
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved pin for internal use. Should be left floating.
Reserved pin for internal use. Should be left floating.
Reserved pin for internal use. Should be left floating.
Reserved pin for internal use. Should be left floating.
Reserved pin for internal use. Should be left floating.
Reserved pin for internal use. Should be left floating.
Reserved pin for internal use. Should be left floating.
Reserved pin for internal use. Should be left floating.
38
41
65
72
124
125
6-Port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller
23
Track ID: JATR-1076-21 Rev. 1.1