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    RTL8306SD-VC-GR 参数 Datasheet PDF下载

    RTL8306SD-VC-GR图片预览
    型号： RTL8306SD-VC-GR
    PDF下载： 下载PDF文件 查看货源
    内容描述： [Micro Peripheral IC]
    分类和应用：
    文件页数/大小： 132 页 / 1325 K
    品牌： REALTEK [ REALTEK ]
     浏览型号RTL8306SD-VC-GR的Datasheet PDF文件第1页浏览型号RTL8306SD-VC-GR的Datasheet PDF文件第2页浏览型号RTL8306SD-VC-GR的Datasheet PDF文件第4页浏览型号RTL8306SD-VC-GR的Datasheet PDF文件第5页浏览型号RTL8306SD-VC-GR的Datasheet PDF文件第6页浏览型号RTL8306SD-VC-GR的Datasheet PDF文件第7页浏览型号RTL8306SD-VC-GR的Datasheet PDF文件第8页浏览型号RTL8306SD-VC-GR的Datasheet PDF文件第9页  
    RTL8306SD/RTL8306SDM
    Datasheet
    Table of Contents
    1.
    2.
    3.
    4.
    5.
    GENERAL DESCRIPTION ..............................................................................................................................................1
    FEATURES .........................................................................................................................................................................3
    SYSTEM APPLICATIONS...............................................................................................................................................4
    BLOCK DIAGRAM ...........................................................................................................................................................5
    PIN ASSIGNMENTS .........................................................................................................................................................6
    5.1.
    5.2.
    5.3.
    6.
    6.1.
    6.2.
    6.3.
    6.4.
    6.5.
    6.6.
    6.7.
    6.8.
    6.9.
    6.10.
    7.
    P
    IN
    A
    SSIGNMENTS
    D
    IAGRAM
    .......................................................................................................................................6
    P
    ACKAGE
    I
    DENTIFICATION
    ...........................................................................................................................................6
    P
    IN
    A
    SSIGNMENTS
    T
    ABLE
    ............................................................................................................................................7
    M
    EDIA
    C
    ONNECTION
    P
    INS
    ...........................................................................................................................................9
    M
    ODE
    C
    ONFIGURATION
    P
    INS
    .......................................................................................................................................9
    P
    ORT
    4 MAC C
    IRCUIT
    I
    NTERFACE
    P
    INS
    ......................................................................................................................13
    P
    ORT
    4 PHY C
    IRCUIT
    I
    NTERFACE
    P
    INS
    ......................................................................................................................16
    M
    ISCELLANEOUS
    P
    INS
    ...............................................................................................................................................23
    P
    ORT
    LED P
    INS
    .........................................................................................................................................................24
    S
    ERIAL
    EEPROM
    AND
    SMI P
    INS
    ..............................................................................................................................26
    S
    TRAPPING
    P
    INS
    .........................................................................................................................................................27
    P
    ORT
    S
    TATUS
    S
    TRAPPING
    P
    INS
    ..................................................................................................................................29
    P
    OWER
    P
    INS
    ...............................................................................................................................................................31
    PIN DESCRIPTIONS.........................................................................................................................................................9
    BASIC FUNCTIONAL DESCRIPTION........................................................................................................................32
    7.1.
    S
    WITCH
    C
    ORE
    F
    UNCTION
    O
    VERVIEW
    .........................................................................................................................32
    7.1.1. Dual MII/RMII .....................................................................................................................................................32
    7.1.2. Port0, 1, 2, 3 Status Configuration.......................................................................................................................35
    7.1.3. Flow Control ........................................................................................................................................................35
    7.1.4. Address Search, Learning, and Aging ..................................................................................................................37
    7.1.5. Half Duplex Operation .........................................................................................................................................38
    7.1.6. InterFrame Gap....................................................................................................................................................38
    7.1.7. Illegal Frame........................................................................................................................................................38
    7.2.
    P
    HYSICAL
    L
    AYER
    F
    UNCTIONAL
    O
    VERVIEW
    ...............................................................................................................39
    7.2.1. Auto-Negotiation for UTP ....................................................................................................................................39
    7.2.2. 10Base-T Transmit Function ................................................................................................................................39
    7.2.3. 10Base-T Receive Function ..................................................................................................................................39
    7.2.4. Link Monitor.........................................................................................................................................................39
    7.2.5. 100Base-TX Transmit Function............................................................................................................................39
    7.2.6. 100Base-TX Receive Function..............................................................................................................................40
    7.2.7. Power-Down Mode...............................................................................................................................................40
    7.2.8. Crossover Detection and Auto Correction ...........................................................................................................40
    7.2.9. Polarity Detection and Correction .......................................................................................................................41
    7.3.
    G
    ENERAL
    F
    UNCTION
    O
    VERVIEW
    ................................................................................................................................42
    7.3.1. Reset .....................................................................................................................................................................42
    7.3.2. Setup and Configuration.......................................................................................................................................43
    7.3.3. Serial EEPROM Example: 24LC01/02/04 ...........................................................................................................44
    7.3.4. SMI .......................................................................................................................................................................46
    7.3.5. Head-Of-Line Blocking ........................................................................................................................................47
    7.3.6. Filtering/Forwarding Reserved Control Frame ...................................................................................................47
    7.3.7. Loop Detection .....................................................................................................................................................48
    7.3.8. MAC Local Loopback Return to External ............................................................................................................49
    6-port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller
    iii
    Track ID: JATR-1076-21 Rev. 1.1

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