RTL8306SD/RTL8306SDM
Datasheet
COPYRIGHT
©2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
TRADEMARKS
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are trademarks/registered trademarks of their respective owners.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
USING THIS DOCUMENT
This document is intended for use by the software engineer when programming for Realtek
RTL8306SD/RTL8306SDM controller chips. Information pertaining to the hardware design of products
using these chips is contained in a separate document.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
1.1
Release Date
2006/11/24
2007/06/22
Summary
First release.
1. Revised Table 1 Pin Assignments Table, page 7 (AI and A0 pin types).
2. Revised Table 5 Port 4 PHY Circuit Interface Pin Definitions, page 16 (Changed
‘DISPORTPRI[4]’ to ‘DISPORTPRI[1]’ for pin 84 description, and changed
‘DISPORTPRI[4]” to ‘DISPORTPRI[0]’ for pin 83 description).
3. Revised Table 8 Serial EEPROM and SMI Pins, page 26 (Changed ‘0 to 25MHz
clock’ to ‘0 to 2.5MHz clock’ for pin 74 description).
4. Revised Table 9 Strapping Pins, page 27 (changed the strapping pin function
description of Pin 111).
5. Revised the MLD description (see section 8.9IGMP & MLD Snooping Function,
page 71).
6. Corrected register names in section 8.14 Port Mirroring, page 80.
7. Added page selection register description (Table 34 PHY 0 Register 16 (Page 0, 1,
8. Revised Table 62 DC Characteristics, page 113.
9. Revised Table 65 MII & SMI DC Timing, page 116.
10. Revised section 14 Ordering Information, page 123.
ii
Track ID: JATR-1076-21 Rev. 1.1
6-port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller
REALTEK [ REALTEK ]
