RTL8306SD/RTL8306SDM
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM..........................................................................................................................................................5
FIGURE 2. PIN ASSIGNMENTS ........................................................................................................................................................6
FIGURE 3. DUAL MII/RMII DIAGRAM .......................................................................................................................................33
FIGURE 4. RESET .........................................................................................................................................................................42
FIGURE 5. START AND STOP DEFINITION .....................................................................................................................................44
FIGURE 6. OUTPUT ACKNOWLEDGE ............................................................................................................................................45
FIGURE 7. RANDOM READ...........................................................................................................................................................45
FIGURE 8. SEQUENTIAL READ .....................................................................................................................................................45
FIGURE 9. LOOP EXAMPLE...........................................................................................................................................................48
FIGURE 10. PORT 4 LOOPBACK .....................................................................................................................................................49
FIGURE 11. REG. 0.14 LOOPBACK .................................................................................................................................................50
FIGURE 12. USING A PNP TRANSISTOR TO TRANSFORM 3.3V INTO 1.8V .....................................................................................51
FIGURE 13. VLAN GROUPING EXAMPLE ......................................................................................................................................55
FIGURE 14. VLAN GROUPING WITH PORT5 MAC IN DUAL-(R)MII MODE ..................................................................................56
FIGURE 15. TAGGED AND UNTAGGED PACKET FORWARDING WHEN 802.1Q TAG AWARE VLAN IS ENABLED ...........................57
FIGURE 16. RTL8306SD/RTL8306SDM PACKET SCHEDULING DIAGRAM..................................................................................59
FIGURE 17. RTL8306SD/RTL8306SDM PRIORITY ASSIGNMENT DIAGRAM ...............................................................................61
FIGURE 18. PACKET PRIORITY SELECTION ....................................................................................................................................64
FIGURE 19. STORM FILTER APPLICATION EXAMPLE .....................................................................................................................69
FIGURE 20. IGMP & MLD APPLICATION EXAMPLE .....................................................................................................................72
FIGURE 21. CPU TAG APPLICATION EXAMPLE .............................................................................................................................74
FIGURE 22. BROADCAST INPUT DROP VS. OUTPUT DROP..............................................................................................................79
FIGURE 23. MULTICAST INPUT DROP VS. OUTPUT DROP...............................................................................................................79
FIGURE 24. FLOATING AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED ........................................................................82
FIGURE 25. TWO-PIN BI-COLOR LED FOR SPD FLOATING OR PULL-HIGH ...................................................................................82
FIGURE 26. TWO-PIN BI-COLOR LED FOR SPD PULL-DOWN........................................................................................................82
FIGURE 27. RECEPTION DATA TIMING OF MII/RMII/SMI INTERFACE........................................................................................115
FIGURE 28. TRANSMISSION DATA TIMING OF MII/RMII/SMI INTERFACE..................................................................................115
FIGURE 29. UTP APPLICATION FOR TRANSFORMER WITH CONNECTED CENTRAL TAP...............................................................118
FIGURE 30. UTP APPLICATION FOR TRANSFORMER WITH SEPARATE CENTRAL TAP ..................................................................119
6-port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller
ix
Track ID: JATR-1076-21 Rev. 1.1
REALTEK [ Realtek Semiconductor Corp. ]
