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RTL8306SD-VC-GR 参数 Datasheet PDF下载

RTL8306SD-VC-GR图片预览
型号: RTL8306SD-VC-GR
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC]
分类和应用:
文件页数/大小: 132 页 / 1325 K
品牌: REALTEK [ Realtek Semiconductor Corp. ]
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RTL8306SD/RTL8306SDM  
Datasheet  
7.3.3.2  
EEPROM Size Selection  
The RTL8306SD/RTL8306SDM supports three serial EEPROM sizes —1k bits, 2k bits and 4k bits. Via  
the auto-download operation, the RTL8306SD/RTL8306SDM decides the size of the data downloaded to  
the RTL8306SD/RTL8306SDM from the EEPROM according to the value of bit 4 and bit 3 of the 77th  
byte data in the serial EEPROM.  
If the bits 77. [4:3] = 11, it is reserved mode; if the bits 77. [4:3] = 10, 01, or 00, it means the data size is  
4k bits, 2k bits, or 1k bits respectively. The value of the two bits should accord with the actual EEPROM  
data size. For example, the value of the bits 77. [4:3] can not be ‘10’ when the 24LC02 is used.  
7.3.4.  
SMI  
The SMI (Serial Management Interface) is also known as the MII Management Interface, and consists of  
two signals (MDIO and MDC). It allows external devices with SMI master mode (MDC is output) to  
control the state of the PHY and internal registers (SMI slave mode: MDC is input). MDC is an input  
clock for the RTL8306SD/RTL8306SDM to latch MDIO on its rising edge. The clock can run from DC  
to 2.5MHz. MDIO is a bi-directional connection used to write data to, or read data from the  
RTL8306SD/RTL8306SDM. The PHY address is from 0 to 6.  
Table 13. SMI Read/Write Cycles  
Preamble  
(32 bits) (2 bits)  
Start  
OP Code  
(2 bits)  
10  
PHYAD  
(5 bits)  
REGAD  
(5 bits)  
Turn Around  
Data  
(16 bits)  
Idle  
(2 bits)  
Z0  
Read  
Write  
1……..1  
1……..1  
01  
01  
A4A3A2A1A0 R4R3R2R1R0  
A4A3A2A1A0 R4R3R2R1R0  
D15…….D0 Z*  
D15…….D0 Z*  
01  
10  
Note: Z*: High-impedance. During idle time MDIO state is determined by an external 1.5Kpull-up resistor.  
The RTL8306SD/RTL8306SDM supports Preamble Suppression, which allows the MAC to issue  
Read/Write Cycles without preamble bits. However, for the first cycle of MII management after power-on  
reset, a 32-bit preamble is needed.  
To guarantee the first successful SMI transaction after power-on reset, the external device should delay at  
least 1second before issuing the first SMI Read/Write Cycle relative to the rising edge of reset.  
6-Port 10/100Mbps Single-Chip Dual MII/RMII Switch Controller  
46  
Track ID: JATR-1076-21 Rev. 1.1