RTL8201E(L)
Datasheet
7.4. Register 3 PHY Identifier Register 2
Table 14. Register 3 PHY Identifier Register 2
Address Name
Description
Mode
RO
Default
110010
000001
0101
3:15~10 OUI_LSB
Organizationally Unique Identifier Bit 19:24
Model Number
3:9~4
3:3~0
Model Number
RO
Revision Number Revision Number
RO
7.5. Register 4 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner
during auto-negotiation.
Table 15. Register 4 Auto-Negotiation Advertisement Register (ANAR)
Address Name
Description
Mode
Default
4:15
NP
Next Page Bit.
RO
0
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
1: Acknowledge reception of link partner capability data word
0: Do not acknowledge reception
4:14
4:13
ACK
RF
RO
0
0
1: Advertise remote fault detection capability
0: Do not advertise remote fault detection capability
Reserved.
RW
4:12~11 Reserved
-
-
4:10
RXFC
1: RX flow control is supported by local node
0: RX flow control not supported by local node
1: 100Base-T4 is supported by local node
0: 100Base-T4 not supported by local node
1: 100Base-TX full duplex is supported by local node
0: 100Base-TX full duplex not supported by local node
1: 100Base-TX is supported by local node
0: 100Base-TX not supported by local node
1: 10Base-T full duplex supported by local node
0: 10Base-T full duplex not supported by local node
1: 10Base-T is supported by local node
0: 10Base-T not supported by local node
RW
0
4:9
T4
RO
RW
RW
RW
RW
RW
0
4:8
TXFD
TX
1
4:7
1
4:6
10FD
10
1
1
4:5
4:4~0
Selector
Binary Encoded Selector Supported by This Node.
Currently only CSMA/CD 00001 is specified. No other protocols
are supported.
00001
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
13
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
