RTL8201E(L)
Datasheet
7.2. Register 1 Basic Mode Status Register
Table 12. Register 1 Basic Mode Status Register
Address Name
Description
Mode Default
1:15
1:14
1:13
1:12
1:11
100Base-T4
1: Enable 100Base-T4 support
RO
RO
RO
RO
RO
0
1
1
1
1
0: Suppress 100Base-T4 support
1: Enable 100Base-TX full duplex support
0: Suppress 100Base-TX full duplex support
1: Enable 100Base-TX half duplex support
0: Suppress 100Base-TX half duplex support
1: Enable 10Base-T full duplex support
0: Suppress 10Base-T full duplex support
1: Enable 10Base-T half duplex support
0: Suppress 10Base-T half duplex support
Reserved.
100Base_TX_ FD
100Base_TX_HD
10Base_T_FD
10_Base_T_HD
1:10~7 Reserved
-
-
1:6
MF Preamble Suppression
The RTL8201E(L) will accept management frames with
preamble suppressed.
RO
1
A minimum of 32 preamble bits are required for the first
SMI read/write transaction after reset. One idle bit is
required between any two management transactions as per
IEEE 802.3u specifications.
1:5
1:4
Auto Negotiation Complete 1: Auto-negotiation process completed
RO
RO
0
0
0: Auto-negotiation process not completed
Remote Fault
1: Remote fault condition detected (cleared on read)
0: No remote fault condition detected
When in 100Base-FX mode, this bit means an in-band
signal Far-End-Fault has been detected (see 8.12 Far End
Fault Indication, page 25).
1:3
1:2
Reserved
Reserved.
-
-
Link Status
1: Valid link established
0: No valid link established
Reserved.
RO
0
1:1~0
Reserved
-
-
7.3. Register 2 PHY Identifier Register 1
Table 13. Register 2 PHY Identifier Register 1
Address Name
Description
Mode Default
RO 001Ch
2:15~0 OUI_MSB
Organizationally Unique Identifier Bit 3:18
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
12
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
