RTL8201E(L)
Datasheet
6.2. RMII Interface (RTL8201E(L)-VB Only)
Table 2. RMII Interface (RTL8201E(L)-VB Only)
Name
Type
IO
Pin No. Pin No. Description
(48-Pin) (32-Pin)
TXC
22
15
Synchronous 50MHz Clock Reference for Receive, Transmit, and
Control Interface. The direction is decided by Register 25.
CRS/RPTR/
CRS_DV
O
36
26
Carrier Sense/Receive Data Valid.
CRS_DV shall be asserted by the PHY when the receive medium is
non-idle.
RXD[0:1]
TXEN
O
I
14, 16
27
9, 10
20
Receive Data.
Transmit Enable.
TXD[0:1]
RXER/FXEN
I
23, 24
39
16, 17 Transmit Data.
28 Receive Error.
O
6.3. SNI (Serial Network Interface) 10Mbps Only
Table 3. SNI (Serial Network Interface) 10Mbps Only
Name
Type
Pin No.
(48-Pin)
Pin No. Description
(32-Pin)
COL/SNI
RXD0
O/PD
O/PD
38
14
36
27
9
Collision Detect.
Received Serial Data.
Carrier Sense.
CRS/RPTR/ O/PD
CRS_DV
26
RXC
O/HZ
I/PD
19
23
22
27
13
16
15
20
Receive Clock. Resolved from received data.
Transmit Serial Data.
TXD0
TXC
O/HZ
I/PD
Transmit Clock. Generated by PHY.
TXEN
Transmit Enable. For MAC to indicate transmit operation.
6.4. Clock Interface
Table 4. Clock Interface
Name
Type
Pin No.
(48-Pin)
Pin No. Description
(32-Pin)
CKXTAL2
O
43
32
25MHz Crystal Output.
This pin provides the 25MHz crystal output. It must be left open
when an external 25MHz oscillator drives X1.
CKXTAL1
I
42
31
25MHz Crystal Input.
This pin provides the 25MHz crystal input. If a 25MHz oscillator is
used, connect CKXTAL1 to the oscillator’s output (see 9.3 Crystal
Characteristics, page 35, for clock source specifications).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
8
Track ID: JATR-1076-21 Rev. 1.3