72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
TAP Controller Block Diagram
0
0
0
0
Bypass Register
2
1
1
1
Instruction Register
Selection
Circuitry
Selection
TDO
TDI
Circuitry
31 30 29
.
.
2
Identification Register
69
.
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 21 of 30