72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
Identification Register Definitions
Instruction Field
Value
Description
Revision Number
(31:29)
XXX
Defines die revision number.
Voltage
(28,24)
X,X
Defines VDD voltage of SRAM – 0,0 (3.3V) and 0,1 (2.5V).
Reserved.
Reserved
(27:25)
XXX
Architecture
(23:21)
001
Defines SRAM architecture (NoBL).
Defines type of SRAM (pipelined burst 4).
Defines width of SRAM.
Memory Type
(20:18)
011
Bus Width
(17:15)
100
Density
(14:12)
100
Defines density of SRAM (64M/72M).
JEDEC Code
(11:1)
000 0011 0010
1
Unique identification of SRAM vendor (32 hex for Enhanced Memory
Systems).
ID Register Presence
(0)
Indicates the presence of an ID register.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 25 of 30
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
