72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
TAP Controller State Diagram
TEST-LOGIC
1
0
RESET
0
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
1
1
1
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
1
0
1
SHIFT-DR
SHIFT-IR
1
1
EXIT1-DR
EXIT1-IR
0
0
0
0
PAUSE-DR
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
0
1
0
NOTE: The 0 or 1 next to each state represents the TMS signal value at the rising edge of TCK.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 20 of 30
Revision 1.0
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
