欢迎访问ic37.com |
会员登录 免费注册
发布采购

SS2625Q1-10 参数 Datasheet PDF下载

SS2625Q1-10图片预览
型号: SS2625Q1-10
PDF下载: 下载PDF文件 查看货源
内容描述: [ZBT SRAM, 2MX36, 5ns, CMOS, PQFP100, TQFP-100]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 30 页 / 223 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
 浏览型号SS2625Q1-10的Datasheet PDF文件第12页浏览型号SS2625Q1-10的Datasheet PDF文件第13页浏览型号SS2625Q1-10的Datasheet PDF文件第14页浏览型号SS2625Q1-10的Datasheet PDF文件第15页浏览型号SS2625Q1-10的Datasheet PDF文件第17页浏览型号SS2625Q1-10的Datasheet PDF文件第18页浏览型号SS2625Q1-10的Datasheet PDF文件第19页浏览型号SS2625Q1-10的Datasheet PDF文件第20页  
72Mbit Pipelined BSRAM  
w/ NoBL Architecture  
2Mx36  
Preliminary Data Sheet  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The SS2625 includes a serial boundary scan Test Access Port (TAP) in the PGBA package only. The TAP is not included  
in the TQFP package. This port functions in accordance with IEEE Standard 1149.1-1990, but does not have the set of  
functions required for full 1149.1 compliance. These functions are excluded because they place an added delay in the  
critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the  
operation of other devices that use 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic  
levels.  
Disabling the JTAG Feature  
The SS2625 can operate without the JTAG feature. To disable the TAP controller, tie TCK to VSS to prevent clocking the  
device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD  
through a pull-up resistor. TDO should be left unconnected. At power-up the device is now in a reset state, which does not  
interfere with device operation.  
Test Access Port (TAP)  
Test Clock (TCK)  
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are  
driven from the falling edge of TCK.  
Test Mode Select (TMS)  
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is  
allowable to leave this pin unconnected if the TAP is not used. This pin is pulled up internally.  
Test Data In (TDI)  
The TDI pin is used to serially input information to the registers. It can be connected to the input of any of the  
registers. Which register is placed between TDI and TDO is determined by the instruction loaded into the TAP  
Instruction register. See the TAP Controller State Diagram for more information. TDI is internally pulled up and can  
be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any  
register.  
Test Data-Out (TDO)  
The TDO output is used to serially output information from the registers. The output is active depending on the current  
state of the TAP state machine. See the TAP Controller State Diagram for more information. The output changes on  
the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.  
Performing a TAP Reset  
A reset is performed by forcing TMS high for five rising edges of TCK. This reset does not affect the operation of the  
SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that  
TDO comes up in a high-z state.  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
Copyright 2001 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Page 16 of 30  
Revision 1.0  
 复制成功!