Preliminary Data Sheet
72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Device Operation
The SS2625 is a synchronous pipelined burst SRAM designed specifically to eliminate wait states during write/read
transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal
is qualified with the Clock Enable input signal (CKE#). If CKE# is high, the clock signal is not recognized and all internal
states are maintained. All synchronous operations are qualified with CKE#. All data outputs pass through output registers
controlled by the rising edge of the clock. Maximum access delay from the clock rise (t
CO
) is 3.5 ns (166 MHz device).
Accesses are initiated by driving all three chip enables (CE1#, CE2, and CE3#) true at the rising edge of the clock. If
CKE# and LD# are driven low, an address presented to the device is latched. The access is either a read or write,
depending on the status of R/W#. BW
[a:d]
# are used to perform byte write operations. Writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous chip enables and an asynchronous Output Enable signal (G#) simplify depth expansion. Reads and
writes are pipelined with a two-clock cycle latency. LD# must be driven low to initiate a new transaction. All reads and
writes are burst operations. The burst is a non-interruptible sequence of four clock cycles. A burst sequence is determined
by the state of the LBO# input signal. Driving LBO# low provides a linear burst order, and driving it high provides an
interleaved burst order.
Burst Read Accesses
A burst read access is initiated when the following conditions are satisfied at clock rise: CKE# is driven low; CE1#, CE2,
and CE3# are all driven true; R/W# is driven high; and LD# is driven low. The address presented to the inputs A
0
-A
x
is
latched into the Address register and presented to the memory core and control logic. The control logic recognizes a read
and allows access to the specified address location. The requested data is allowed to propagate to the data bus within 3.5
ns (166 MHz device) provided G# is driven low. The SS2625 has an on-chip burst counter that is incremented on the
rising edge of the clock when LD# is driven high. The device sequences through four address locations for each burst read
access.
Once the burst sequence is completed a new read access can be initiated as described above. Reads can be pipelined such
that data flows out of the device on every clock edge.
The burst counter uses A0 and A1 in the burst sequence and wraps around when incremented more than four times. See
the burst order tables for the burst sequence. The burst sequence is determined by the state of the LBO# input signal. This
signal is a strap pin and must remain static during device operation.
Burst Write Accesses
A burst write access is initiated when the following conditions are satisfied at clock rise: CKE# is driven low; CE1#, CE2,
and CE3# are all driven true; R/W# is driven low; and LD# is driven low. The address presented to the inputs A
0
-A
x
is
loaded into the Address register and the byte write signals are latched into the control logic block.
On the next rising clock edge the data lines are automatically three-stated regardless of the state of the G# input signal.
This allows the external logic to present the data on DQ
[a:d]
.
On the next rising clock edge the data presented to DQ
[a:d]
inputs (or a subset for byte write operations, see the Write Cycle
Description table for details) is latched into the device and stored into the specified address location.
Data written during a write operation is controlled by BW
[a:d]
# signals. The SS2625 provides byte write capability (see the
Write Cycle Description table for details). Driving the R/W# input low with the appropriate BW
[a:d]
# input selectively
writes to the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed
write mechanism is provided to simplify write operations. Byte write capability is included to greatly simplify read-
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
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