Preliminary Data Sheet
72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Description
The Enhanced Memory Systems SS2625 is a 72-Mbit
synchronous pipelined burst SRAM designed specifically to
support back-to-back read/write operations without the
insertion of wait states. The device is organized as 2Mx36
and is offered in 3.3V and 2.5V versions. They are designed
to transfer data on every clock cycle. This feature
dramatically improves throughput, especially in systems that
require frequent write/read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The clock input is qualified by the Clock Enable signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the rising
edge of the clock is 3.5 ns (166 MHz device).
Write operations are controlled by the four Byte Write Select
signals and a Read/Write signal. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enable signals and an asynchronous
Output Enable signal provide for easy depth expansion and
output three-state control. To avoid bus contention, the output
drivers are synchronously three-stated during the data portion
of a write sequence.
Features
•
•
•
•
•
•
•
High Density 72-Mbit
166 MHz bus operations with zero wait states –
Data is transferred on every clock
Fully Registered for Pipelined Operation
User Selectable Linear or Interleaved Burst Order
Byte Write Capability
Single 2.5V or 3.3V Power Supply
Fast Clock to Output Times
•
3.5 ns (for 166 MHz device)
•
4.2 ns (for 133 MHz device)
•
5.0 ns (for 100 MHz device)
Clock Enable pin to Suspend Operations
Synchronous Self Timed Writes
Asynchronous Output Enable
JEDEC Standard 100-pin TQFP & 119-pin PBGA
Low Standby Power
JTAG 1149.1 Compliant Boundary Scan
•
•
•
•
•
•
Block Diagram
36
CLK
Data-In
/CE
Reg.
LD#
Addr
CKE#
CE1#
CE2
CE3#
R/W#
BW#(a:d)
CONTROL
and WRITE
LOGIC
Memory
Array
36
OUTPUT
REGISTERS
and LOGIC
2Mx36
36
DQ(a:d)
G#
This is a product in sampling or pre-production phase of development. Char-
acteristic data and other specifications are subject to change without notice.
Revision 1.0
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
Page 1 of 30
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
