operations during precharge and refresh cycles to minimize wait
states. It is only necessary to select /S and /G and provide the
appropriate column address to read data as shown in the table
below. In this mode of operation, the cache reads will occur from
the page and bank accessed during the last /RE active read cycle.
To perform a cache read in static column mode, /CAL is held high,
and the cache contents at the specified column address will be
valid at time t
AC
after address is stable. To perform a cache read in
page mode, /CAL is clocked to latch the column address. When /RE
is inactive, the hit pin is not driven and is in a high impedance
state.
This option is desirable when the external control logic is
capable of fast hit/miss comparison. In this case, the controller can
avoid the time required to perform row/column multiplexing on hit
cycles.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles where /S can be disabled.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, an /RE only refresh may
be performed using an externally supplied row address. /RE
refresh is performed by executing a
write cycle
(W/R, /G, and /F
are high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
Function
/S
/G
/CAL
A
0-7
operation. All combinations of addresses A
0-9
must be sequenced
every 64ms refresh period. A
10
does not need to be cycled. Read
Cache Read (Static Column)
L
L
H
Col Adr
refresh cycles are not allowed because a DRAM refresh cycle does
Cache Read (Page Mode)
L
L
¤
Col Adr
not occur when a read refresh address matches the LRR address
latch.
EDO Mode and Output Latch Enable Operation
The QLE and /CAL inputs can be used to create extended data
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
output (EDO) mode timings in either static column or page modes.
mode, the internal DRAM circuitry is powered down to reduce
The DM512K32DT6 has an output latch enable (QLE) that can be
used to extend the data output valid time. The output latch enable
standby current.
operates as shown in the following table.
Initialization Cycles
When QLE is low, the latch is transparent and the EDRAM
A minimum of eight /RE active initialization cycles (read,
operates identically to the standard EDRAMs. When /CAL is high
write, or refresh) are required before normal operation is
during a static column mode read, the QLE input can be used to
guaranteed. Following these start-up cycles, two read cycles to
latch the output to extend the data output valid time. QLE can be
different row addresses must be performed for each of the four
held high during page mode reads. In this case, the data outputs
internal banks of DRAM to initialize the internal cache logic. Row
are latched while /CAL is high and open when /CAL is not high.
address bits A
8
and A
9
define the four internal DRAM banks.
Unallowed Mode
QLE
/CAL
Comments
Read, write, or /RE only refresh operations must not be
performed to unselected memory banks by clocking /RE when /S is
L
X
Output Transparent
high.
¤
H
Output Latched When QLE=H (Static Column EDO)
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to
H
¤
Output Latched When /CAL=H (Page Mode EDO)
optimize system performance, the interface to the EDRAM may be
simplified to reduce the number of control lines by either tying pins
Write-Per-Bit Operation
to ground or by tying one or more control inputs together. The /S
The DM512K72 DIMM offers a write-per-bit capability to
input can be tied to ground if the low power standby mode is not
selectively modify individual parity bits (DQ
8, 17, 26, 35, 44, 53, 62, 71
)
required. The QLE input can be tied low if output latching is not
for byte write operations. The parity device (DM2213) is selected
required, or it can be tied high if “extended data out” (hyper page
via /CAL
8
. Byte write selection to non-parity bits is accomplished via
mode) is required. The /HIT output pin is not necessary for device
/CAL
0-7
. The bits to be written are determined by a bit mask data
operation. The W/R and /G inputs can be tied together if reads are
word which is placed on the parity I/O data pins prior to clocking
not required during a write hit cycle. The simplified control interface
/RE. The logic one bits in the mask data select the bits to be
still allows the fast page read/write cycle times, fast random read/
written. As soon as the mask is latched by /RE, the mask data is
write times, and hidden precharge functions available with the EDRAM.
removed and write data can be placed on the data bus. The mask is
only specified on the /RE transition. During page mode burst write
Pin Descriptions
operations, the same mask is used for all write operations.
/RE — Row Enable
These inputs are used to initiate DRAM read and write
ECC Operation
operations and latch a row address. It is not necessary to clock /RE
The DM512K72DT6-xxN supports error correction coding
to read data from the EDRAM SRAM row register. On read
(ECC) by replacing the parity chip with a normal DM2203 device.
operations, /RE can be brought high as soon as data is loaded into
This version does not support write-per-bit parity operation.
cache to allow early precharge.
2-140
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
