refresh bus allows the EDRAM to be refreshed during cache reads.
Memory writes can be posted as early as 6.5ns after row
enable and are directed to the DRAM array. During a write hit, the
on-chip address comparator activates a parallel write path to the
SRAM cache to maintain coherency. Memory writes do not affect
the contents of the cache row register except during write hits.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior system performance at less cost, power, and
area than systems implemented with complex synchronous SRAM
cache, cache controllers, and multilevel data busses.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select row address bits A
8
and A
9
. The contents of these cache row
registers is always equal to the last row that was read from each of
the four internal DRAM banks (as modified by any write hit data).
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
last row read address latch for the bank specified by row address
bits A
8-9
(LRR: a 9-bit row address latch for each internal DRAM
bank which is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the row and column address is available at the output
pins at the greater of times t
AC
or t
GQV
. The /HIT output is driven
low at time t
HV
after /RE to indicate the shorter access time to the
Functional Description
The EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM
to hide precharge and refresh operation during reads and
maximize hit rate by maintaining page cache contents during write
operations even if data is written to another memory page. These
capabilities, in conjunction with the faster basic DRAM and cache
speeds of the EDRAM, minimize processor wait states.
Four Bank Cache Architecture
HIT0
HIT1
HIT2
HIT3
Bank 3
Bank 2
Bank 1
Bank 0
/HIT
Row Address Latch
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA
0-10
Column Address Latch
CA
0-7
1M Array
1M Array
1M Array
1M Array
D
0-71
A
0-10
Data-In
Latch
256 x 72
Cache
Bank 0
CA
0-7
256 x 72
Cache
Bank 1
256 x 72
Cache
Bank 2
256 x 72
Cache
Bank 3
(0,0)
RA
8
, RA
9
(0,1)
(1,0)
(1,1)
1 of 4 Selector
CAL
QLE
Data-Out
Latch
G
S
Q
0-71
2-138
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
