Buffer Diagrams
DIMM Edge
Connector
U11C
U10B
34
A10 Bank0A
33
A10 Bank0B
38
A10 36
31
A10 Bank0C
30
A10 Bank0D
41
A9 Bank0A
40
A9 Bank0B
121
A9 42
38
A9 Bank0C
37
A9 Bank0D
29
33
A0 21
16
17
31
/G 15
19
/G Bank0A
/G Bank0B
/G Bank0C
20
/G Bank0D
23
A0 Bank0A
24
A0 Bank0B
26
A0 Bank0C
27
A0 Bank0D
28
U11D
U10C
48
A7 Bank0A
47
A7 Bank0B
120
A7 43
45
A7 Bank0C
44
A7 Bank0D
55
A5 Bank0A
54
A5 Bank0B
119
A5 49
52
A5 Bank0C
51
A5 Bank0D
58
117
A1 42
118
A3 36
34
A3 Bank0A
33
A3 Bank0B
31
A3 Bank0C
30
A3 Bank0D
41
A1 Bank0A
40
A1 Bank0B
38
A1 Bank0C
37
A1 Bank0D
29
U10D
IDT74FCT162344ETPA
U10A
2
/WE Bank0A
3
/WE Bank0B
27
/WE 8
5
/WE Bank0C
6
/WE Bank0D
9
10
30
/S 14
/S Bank0A
/S Bank0B
/S Bank0C
/S Bank0D
48
W/R Bank0A
47
W/R Bank0B
115
W/R 43
45
W/R Bank0C
44
W/R Bank0D
55
54
111
/F 49
52
51
58
/F Bank0A
/F Bank0B
/F Bank0C
VDD
4
11
18
25
32
39
7 Vcc
22 Vcc
35 Vcc
50 Vcc
12
13
1
.22µf
/F BankOD
46
53
Note: Address and control buffers add a minimum of 1.5ns and a maximum of 3.8ns delay to each signal path.
2-145
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
