external control logic. Since no DRAM activity is initiated, /RE can
be brought high after time t
RE1
, and a shorter precharge time, t
RP1
,
is required. Additional locations within the currently active page
may be accessed concurrently with precharge by providing new
column addresses to the multiplex address inputs. New data is
available at the output at time t
AC
after each column address change
in static column mode. During any read cycle, it is possible to
operate in either static column mode with /CAL=high or page
mode with /CAL clocked to latch the column address. In page
mode, data valid time is determined by either t
AC
and t
CQV
.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
LRR address latch for the bank specified by row address bits A
8-9
(LRR: a 9-bit row address latch for each internal DRAM bank
which is reloaded on each /RE active read miss cycle). If the row
address does not match the LRR, the requested data is not in SRAM
cache and a new row is fetched from the DRAM. The EDRAM will
load the new row data into the SRAM cache and update the LRR
latch. The data at the specified column address is available at the
output pins at the greater of times t
RAC
, t
AC
, and t
GQV
. The /HIT
output is driven high at time t
HV
after /RE to indicate the longer
access time to the external control logic. /RE may be brought high
after time t
RE
since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
data is accessed from SRAM cache. Additional locations within the
currently active page may be accessed by providing new column
addresses to the multiplex address inputs. New data is available at
the output at time t
AC
after each column address change in static
column mode. During any read cycle, it is possible to operate in
either static column mode with /CAL=high or page mode with /CAL
clocked to latch the column address. In page mode, data valid time
is determined by either t
AC
and t
CQV
.
DRAM Write Hit
A DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified by row
address bits A
8-9
(LRR: a 9-bit row address latch for each internal
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address matches the LRR, the EDRAM will write data to
both the DRAM page in the appropriate bank and its corresponding
SRAM cache simultaneously to maintain coherency. The write
/RE Inactive Operation
address and data are posted to the DRAM as soon as the column
Data may be read from the SRAM cache without clocking /RE.
address is latched by bringing /CAL low and the write data is latched This capability allows the EDRAM to perform cache read
EDRAM Basic Operating Modes
Function
Read Hit
Read Miss
Write Hit
Write Miss
Internal Refresh
Low Power Standby
Unallowed Mode
by bringing /WE low (both /CAL and /WE must be high when
initiating the write cycle with the falling edge of /RE). The write
address and data can be latched very quickly after the fall of /RE
(t
RAH
+ t
ASC
for the column address and t
DS
for the data). During a
write burst sequence, the second write data can be posted at time
t
RSW
after /RE. Subsequent writes within a page can occur with write
cycle time t
PC
. With /G enabled and /WE disabled, read operations
may be performed while /RE is activated in write hit mode. This
allows read-modify-write, write-verify, or random read-write
sequences within the page with 12ns cycle times. During a write hit
sequence, the /HIT output is driven low. At the end of any write
sequence (after /CAL and /WE are brought high and t
RE
is satisfied),
/RE can be brought high to precharge the memory. Cache reads can
be performed concurrently with precharge (see “/RE Inactive
Operation”). When /RE is inactive, the cache reads will occur from
the page accessed during the last /RE active read cycle.
DRAM Write Miss
A DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified for row
address bits A
8-9
(LRR: a 9-bit row address latch for each internal
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address does not match any of the LRRs, the EDRAM will
write data to the DRAM page in the appropriate bank and the
contents of the current cache is not modified. The write address and
data are posted to the DRAM as soon as the column address is
latched by bringing /CAL low and the write data is latched by
bringing /WE low (both /CAL and /WE must be high when initiating
the write cycle with the falling edge of /RE). The write address and
data can be latched very quickly after the fall of /RE (t
RAH
+ t
ASC
for
the column address and t
DS
for the data). During a write burst
sequence, the second write data can be posted at time t
RSW
after
/RE. Subsequent writes within a page can occur with write cycle
time t
PC
. During a write miss sequence, the /HIT output is driven
high, cache reads are inhibited, and the output buffers are disabled
(independently of /G) until time t
WRR
after /RE goes high. At the end
of a write sequence (after /CAL and /WE are brought high and t
RE
is
satisfied), /RE can be brought high to precharge the memory. Cache
reads can be performed concurrently with the precharge (see “/RE
Inactive Operation”). When /RE is inactive, the cache reads will
occur from the page accessed during the last /RE active read cycle.
/S
L
L
L
L
X
H
H
/RE
↓
↓
↓
↓
↓
H
L
W/R
L
L
H
H
X
X
X
/F
H
H
H
H
L
X
H
A
0-10
Row = LRR
Row
≠
LRR
Row = LRR
Row
≠
LRR
X
X
X
Standby Current
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
H = High; L = Low; X = Don’t Care;
↓
= High-to-Low Transition; LRR = Last Row Read
2-139
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
