QN8007B/8007LB
0
CCA_INT_EN
0
TX CCA Interrupt Enable: When CCA_INT_EN=1, a 4.5ms low pulse will
be output from DOUT/INT (TX mode) when TXCCA is finished.
0
1
Disable
Enable
Word: RDSD0 Address: 10h (RW)
Bit 7
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSB)
rdsd0[7]
rw
rdsd0[6]
rw
rdsd0[5]
rw
rdsd0[4]
rw
rdsd0[3]
rw
rdsd0[2]
rw
rdsd0[1]
rw
rdsd0[0]
rw
Bit
Symbol
RDSD0[7:0]
Default
0000 0000
Description
7:0
RDS data byte 0: Data written into RDSD0~RDSD7 cannot be read out
unless RDSTXRDY is toggled to allow the data to be loaded into the
internal transmitting buffer.
Word: RDSD1 Address: 11h (RW)
Bit 7
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSB)
rdsd1[7]
rw
rdsd1[6]
rw
rdsd1[5]
rw
rdsd1[4]
rw
rdsd1[3]
rw
rdsd1[2]
rw
rdsd1[1]
rw
rdsd1[0]
rw
Bit
Symbol
RDSD1[7:0]
Default
0000 0000
Description
7:0
RDS data byte 1
Rev 2.09 (11/09)
Confidential A
Copyright ©2009 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
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