QN8007B/8007LB
Word: STATUS1 Address: 1Ah (RO)
Bit 7
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSB)
rsvd
ro
(LSB)
rsvd
ro
rsvd
ro
i2sovfl
ro
i2sundfl
ro
insat
ro
rsvd
ro
rsvd
ro
Bit
Symbol
Default
Description
7:6
5
rsvd
rr
r
Reserved
I2S overflow indicator:
I2SOVFL
0
1
No overflow
Overflow
4
3
I2SUNDFL
INSAT
rsvd
r
r
I2S underflow indicator:
0
1
No underflow
Underflow
Input level saturation flag:
0
1
No saturation
Input level too high, Channel saturates.
2:0
rr
Reserved
Word: STATUS2 Address: 1Bh (RO)
Bit 7
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSB)
rds_rxtxupd
ro
rsvd
ro
rsvd
ro
rsvd
ro
rsvd
ro
rsvd
ro
rsvd
ro
rsvd
ro
Bit
value
Symbol
Description
7
r
RDS_RXTXUPD RDS RX: RDS received group updated. Each time a new group is received, this
bit will be toggled.
RDS TX: If user want the chip transmitting all the 8 bytes in RDS0~RDS7, user
should toggle the register bit RDSTXRDY. Then the chip internally will fetch
these bytes after completing transmitting of current group. Once the chip
internally fetched these bytes, it will toggle this bit.
If RDS_INT_EN=1, then at the same time this bit is toggled, interrupt output will
out put a 4.5 ms low pulse.
RDS_RXTXUPD
Status
Rev 2.09 (11/09)
Confidential A
Copyright ©2009 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
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