Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
Parameter
Symbol
DDR2–533
Min.
Unit
Note
1)2)3)4)5)6)7)
Max.
Data hold skew factor
tQHS
tREFI
tREFI
tRFC
—
400
7.8
3.9
—
ps
µs
µs
ns
14)15)
16)18)
17)
Average periodic refresh Interval
Average periodic refresh Interval
—
—
Auto-Refresh to Active/Auto-Refresh
command period
127.5
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1tCK
—
ns
ns
tCK
tCK
ns
tRP
15 + 1tCK
0.9
—
14)
tRPRE
tRPST
tRRD
1.1
0.60
—
14)
Read postamble
0.40
14)18)
Active bank A to Active bank B command
period
7.5
16)22)
Active bank A to Active bank B command
period
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
ns
tCK
tCK
ns
tWPRE
tWPST
tWR
0.25
0.40
15
—
19)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
20)
21)
Internal Write to Read command delay
tWTR
7.5
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
WR
t
RFC +10
200
WR/tCK
—
—
—
ns
tCK
tCK
22)
Write recovery time for write with Auto-
Precharge
t
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
Rev. 1.0, 2006-11
25
11172006-DXYK-2PPW
QIMONDA [ QIMONDA AG ]
