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HYS64T256022EDL-2.5-B 参数 Datasheet PDF下载

HYS64T256022EDL-2.5-B图片预览
型号: HYS64T256022EDL-2.5-B
PDF下载: 下载PDF文件 查看货源
内容描述: 200针双芯片小外形- DDR2 -SDRAM模块 [200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 40 页 / 2384 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B  
Small Outline DDR2 SDRAM Modules  
Parameter  
Symbol Note  
1)2)3)4)5)  
Distributed Refresh Current  
IDD5D  
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Self-Refresh Current  
IDD6  
CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data  
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.  
6)  
All Bank Interleave Read Current  
IDD7  
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control  
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.  
1)  
2)  
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V  
IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.  
3) Definitions for IDD see Table 21  
4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P  
5) For details and notes see the relevant Qimonda component data sheet  
6)  
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output  
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.  
TABLE 21  
Definitions for IDD  
Parameter  
LOW  
Description  
VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN  
Inputs are stable at a HIGH or LOW level  
Inputs are VREF = VDDQ /2  
STABLE  
FLOATING  
SWITCHING  
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control  
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ  
signals not including mask or strobes  
Rev. 1.0, 2006-11  
29  
11172006-DXYK-2PPW  
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