Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
3.3.2
Component AC Timing Parameters
Timing Parameters: Table 15 for DDR2–800, Table 16 for DDR2–667D and Table 17 for DDR2–533C
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
9)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
tAC
–400
2
+400
—
ps
tCCD
nCK
tCK.AVG
ps
10)11)
10)11)
12)
tCH.AVG
tCK.AVG
0.48
2500
3
0.52
8000
—
CKE minimum pulse width ( high and low pulse tCKE
nCK
width)
10)11)
13)14)
Average clock low pulse width
tCL.AVG
0.48
0.52
—
tCK.AVG
nCK
ns
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK .AVG
tIH
+
—
19)20)15)
9)
DQ and DM input hold time
tDH.BASE
tDIPW
tDQSCK
tDQSH
125
—
ps
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
0.35
–350
0.35
0.35
—
—
tCK.AVG
ps
+350
—
tCK.AVG
tCK.AVG
ps
DQS input low pulse width
tDQSL
—
16)
17)
DQS-DQ skew for DQS & associated DQ signals tDQSQ
200
+ 0.25
DQS latching rising transition to associated clock tDQSS
– 0.25
tCK.AVG
edges
18)19)20)
17)
DQ and DM input setup time
tDS.BASE
tDSH
tDSS
50
—
—
—
—
—
__
ps
DQS falling edge hold time from CK
DQS falling edge to CK setup time
0.2
0.2
35
tCK.AVG
tCK.AVG
ns
17)
31)
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
31)
45
ns
21)
CK half pulse width
tHP
Min(tCH.ABS
,
ps
tCL.ABS
)
9)22)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
23)25)
tIH.BASE
250
0.6
ps
Control & address input pulse width for each input tIPW
—
tCK.AVG
ps
24)25)
9)22)
9)22)
31)
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
tIS.BASE
175
—
tLZ.DQ
tLZ.DQS
tMOD
tMRD
tOIT
2 × tAC.MIN
tAC.MAX
tAC.MAX
12
ps
tAC.MIN
ps
0
2
0
ns
—
nCK
ns
31)
26)
12
DQ/DQS output hold time from DQS
tQH
t
HP – tQHS
—
ps
Rev. 1.0, 2006-11
17
11172006-DXYK-2PPW
QIMONDA [ QIMONDA AG ]
