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HYS64T256022EDL-2.5-B 参数 Datasheet PDF下载

HYS64T256022EDL-2.5-B图片预览
型号: HYS64T256022EDL-2.5-B
PDF下载: 下载PDF文件 查看货源
内容描述: 200针双芯片小外形- DDR2 -SDRAM模块 [200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 40 页 / 2384 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B  
Small Outline DDR2 SDRAM Modules  
3.2  
DC Operating Conditions  
TABLE 10  
Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Max.  
Operating temperature (ambient)  
DRAM Case Temperature  
TOPR  
TCASE  
TSTG  
0
+65  
+95  
+100  
+105  
90  
°C  
°C  
°C  
kPa  
%
1)2)3)4)  
5)  
0
Storage Temperature  
– 50  
+69  
10  
Barometric Pressure (operating & storage)  
Operating Humidity (relative)  
PBar  
HOPR  
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.  
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported  
3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs  
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by  
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%.  
5) Up to 3000 m.  
TABLE 11  
Supply Voltage Levels and DC Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Typ.  
Max.  
Device Supply Voltage  
Output Supply Voltage  
Input Reference Voltage  
SPD Supply Voltage  
VDD  
1.7  
1.8  
1.9  
V
1)  
2)  
VDDQ  
VREF  
1.7  
1.8  
1.9  
V
0.49 × VDDQ  
0.5 × VDDQ  
0.51 × VDDQ  
V
VDDSPD  
VIH(DC)  
VIL (DC  
IL  
1.7  
3.6  
V
DC Input Logic High  
VREF + 0.125  
V
V
5
DDQ + 0.3  
V
DC Input Logic Low  
)
– 0.30  
– 5  
REF – 0.125  
V
3)  
In / Output Leakage Current  
µA  
1) Under all conditions, VDDQ must be less than or equal to VDD  
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ  
3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin  
.
Rev. 1.0, 2006-11  
13  
11172006-DXYK-2PPW  
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