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HYS64T256022EDL-2.5-B 参数 Datasheet PDF下载

HYS64T256022EDL-2.5-B图片预览
型号: HYS64T256022EDL-2.5-B
PDF下载: 下载PDF文件 查看货源
内容描述: 200针双芯片小外形- DDR2 -SDRAM模块 [200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 40 页 / 2384 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B  
Small Outline DDR2 SDRAM Modules  
32) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.  
TABLE 16  
DRAM Component Timing Parameter by Speed Grade - DDR2–667  
Parameter  
Symbol  
DDR2–667  
Unit  
Note  
1)2)3)4)5)6)7)8)  
Min.  
Max.  
9)  
DQ output access time from CK / CK  
CAS to CAS command delay  
Average clock high pulse width  
Average clock period  
tAC  
–450  
2
+450  
ps  
tCCD  
nCK  
tCK.AVG  
ps  
10)11)  
12)  
tCH.AVG  
tCK.AVG  
0.48  
3000  
3
0.52  
8000  
CKE minimum pulse width ( high and low pulse tCKE  
nCK  
width)  
10)11)  
13)14)  
Average clock low pulse width  
tCL.AVG  
0.48  
0.52  
tCK.AVG  
nCK  
ns  
Auto-Precharge write recovery + precharge time tDAL  
WR + tnRP  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tIS + tCK .AVG  
tIH  
+
19)20)15)  
9)  
DQ and DM input hold time  
tDH.BASE  
tDIPW  
tDQSCK  
tDQSH  
175  
ps  
DQ and DM input pulse width for each input  
DQS output access time from CK / CK  
DQS input high pulse width  
0.35  
–400  
0.35  
0.35  
tCK.AVG  
ps  
+400  
tCK.AVG  
tCK.AVG  
ps  
DQS input low pulse width  
tDQSL  
16)  
17)  
DQS-DQ skew for DQS & associated DQ signals tDQSQ  
240  
+ 0.25  
DQS latching rising transition to associated clock tDQSS  
– 0.25  
tCK.AVG  
edges  
18)19)20)  
17)  
DQ and DM input setup time  
tDS.BASE  
tDSH  
tDSS  
100  
0.2  
0.2  
37.5  
50  
––  
ps  
DQS falling edge hold time from CK  
DQS falling edge to CK setup time  
tCK.AVG  
tCK.AVG  
ns  
17)  
31)  
Four Activate Window for 1KB page size products tFAW  
Four Activate Window for 2KB page size products tFAW  
31)  
ns  
21)  
CK half pulse width  
tHP  
Min(tCH.ABS  
,
ps  
tCL.ABS  
)
9)22)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
tAC.MAX  
ps  
25)23)  
tIH.BASE  
275  
0.6  
ps  
Control & address input pulse width for each input tIPW  
tCK.AVG  
ps  
24)25)  
9)22)  
9)22)  
31)  
Address and control input setup time  
DQ low impedance time from CK/CK  
DQS/DQS low-impedance time from CK / CK  
MRS command to ODT update delay  
Mode register set command cycle time  
OCD drive mode output delay  
tIS.BASE  
200  
tLZ.DQ  
tLZ.DQS  
tMOD  
tMRD  
tOIT  
2 × tAC.MIN  
tAC.MAX  
tAC.MAX  
12  
ps  
tAC.MIN  
ps  
0
2
0
ns  
nCK  
ns  
31)  
26)  
27)  
12  
DQ/DQS output hold time from DQS  
DQ hold skew factor  
tQH  
t
HP tQHS  
ps  
tQHS  
340  
ps  
Rev. 1.0, 2006-11  
20  
11172006-DXYK-2PPW