Preliminary Internet Data Sheet
HYI25DC512[16/80]0CE
512-Mbit Double-Data-Rate SDRAM
TABLE 21
IDD Specification
Symbol
–6
–5
Unit
Note1)
DDR333
DDR400B
IDD0
IDD1
70
75
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
×8 2)3)
×16 3)
×8 3)
×16 3)
3)
85
90
80
85
95
110
4.6
30
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
4.6
25
3)
3)
3)
22
23
15
16
37
42
×83)
40
45
×16 3)
×8 3)
×16 3)
×8 3)
IDD4R
IDD4W
85
90
115
90
135
95
120
175
5
135
190
5
×16 3)
3)
IDD5
IDD6
IDD7
4)
205
230
230
250
×83)
×16 3)
1) Test conditions : VDD = 2.7 V, TA = 10 °C
2) DD specifications are tested after the device is properly initialized and measured at 200 MHz.
I
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
Rev. 0.7, 2006-12
25
11292006-TAIE-H645
QIMONDA [ QIMONDA AG ]
