Data Sheet.
HY[B/E]18L512160BF-7.5
512-Mbit Mobile-RAM
Parameter
Symbol
- 7.5
Unit
Notes1)2)3)4)
min.
max.
7)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
Refresh period (8192 rows)
Self refresh exit time
tRC
67
19
15
45
14
19
—
1
—
—
—
ns
7)
7)
7)
8)
7)
tRCD
tRRD
tRAS
tWR
tRP
tREF
tSREX
ns
ns
ns
ns
ns
ms
tCK
100k
—
—
64
—
—
—
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (ext.); VDD = VDDQ = 1.70 V to 1.95 V;
2) All parameters assumes proper device initialization.
3) AC timing tests measured at 0.9 V.
4) The transition time is measured between VIH and VIL; all AC characteristics assume tT = 1 ns.
5) Specified tAC and tOH parameters are measured with a 30 pF capacitive load only as shown in Figure 47.
6) If tT > 1 ns, a value of [0.5 x(tT - 1)] ns has to be added to this parameter.
7) These parameter account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified
delay / clock period; round up to next integer.
8) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when fCK ≤ 72 MHz. With fCK > 72 MHz
two clock cycles for tWR are mandatory. Qimonda Technologies recommends to use two clock cycles for the write recovery time in all
applications.
FIGURE 47
I/O
30 pF
3.3
Operating Currents
TABLE 27
Maximum Operating Currents
Parameter & Test Conditions
Symbol
Valuea
Unit
Notes1)
- 7.5
2)3)
Operating current:
one bank: active / read / precharge, BL = 1, tRC = tRCmin
IDD1
120
mA
Precharge power-down standby current:
IDD2P
1.2
1.0
mA
mA
–
all banks idle, CS ≥ VIHmin, CKE ≤ VILmax
,
inputs changing once every two clock cycles
Precharge power-down standby current with clock stop:
all banks idle, CS ≥ VIHmin, CKE ≤ VILmax, all inputs stable
IDD2PS
–
Rev. 1.22, 2006-12
49
01132005-06IU-IGVM
QIMONDA [ QIMONDA AG ]
